document_title: CPU cache

question_text: how many levels of cache memory in the intel i7 processor

question_tokens: how many levels of cache memory in the intel i7 processor

text: CPU cache

text: Overview[edit]

text: When the processor needs to read from or write to a location in main memory, it first checks whether a copy of that data is in the cache. If so, the processor immediately reads from or writes to the cache, which is much faster than reading from or writing to main memory.

text: Most modern desktop and server CPUs have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. A single TLB could be provided for access to both instructions and data, or a separate Instruction TLB (ITLB) and data TLB (DTLB) can be provided.[3] The data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.; see also multi-level caches below). However, the TLB cache is part of the memory management unit (MMU) and not directly related to the CPU caches.

text: Cache entries[edit]

text: Data is transferred between memory and cache in blocks of fixed size, called cache lines or cache blocks. When a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (called a tag).

text: When the processor needs to read or write a location in main memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss has occurred. In the case of a cache hit, the processor immediately reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory, then the request is fulfilled from the contents of the cache.

text: Policies[edit]

text: Replacement policies[edit]

text: In order to make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic that it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there is no perfect way to choose among the variety of replacement policies available. One popular replacement policy, least-recently used (LRU), replaces the least recently accessed entry.

text: Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids the overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on the context.

text: Write policies[edit]

text: If data is written to the cache, at some point it must also be written to main memory; the timing of this write is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to the main memory, and the cache instead tracks which locations have been written over, marking them as dirty. The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read the new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for the new memory location.

text: There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so that multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization).

text: Cached data from the main memory may be changed by other entities (e.g. peripherals using direct memory access (DMA) or another core in a multi-core processor), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a multiprocessor system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep the data consistent are known as cache coherence protocols.

text: Cache performance[edit]

text: Cache performance measurement has become important in the recent times where the speed gap between the memory performance and the processor performance is increasing exponentially. The cache was introduced to reduce this speed gap. Thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important, especially in high-performance systems. The cache hit rate and the cache miss rate play an important role in determining this performance. To improve the cache performance, reducing the miss rate becomes one of the necessary steps among other steps. Decreasing the access time to the cache also gives a boost to its performance.

text: CPU stalls[edit]

text: The time taken to fetch one cache line from memory (read latency due to a cache miss) matters because the CPU will run out of things to do while waiting for the cache line. When a CPU reaches this state, it is called a stall. As CPUs become faster compared to main memory, stalls due to cache misses displace more potential computation; modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory.

text: Various techniques have been employed to keep the CPU busy during this time, including out-of-order execution in which the CPU (Pentium Pro and later Intel designs, for example) attempts to execute independent instructions after the instruction that is waiting for the cache miss data. Another technology, used by many processors, is simultaneous multithreading (SMT), or—in Intel's terminology—hyper-threading (HT), which allows an alternate thread to use the CPU core while the first thread waits for required CPU resources to become available.

text: Cache entry structure[edit]

text: Cache row entries usually have the following structure:

text:
tag
data block
flag bits

text: The data block (cache line) contains the actual data fetched from the main memory. The tag contains (part of) the address of the actual data fetched from the main memory. The flag bits are discussed below.

text: The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache. (The tag, flag and error correction code bits are not included in the size,[4] although they do affect the physical area of a cache.)

text: An effective memory address which goes along with the cache line (memory block) is split (MSB to LSB) into the tag, the index and the block offset.[5][6]

text:
tag
index
block offset

text:
The index describes which cache row (which cache line) that the data has been put in. The index length is

⌈

log

2

(
r
)
⌉

{\displaystyle \lceil \log _{2}(r)\rceil }

 bits for r cache rows.

text:
The block offset specifies the desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is

⌈

log

2

(
b
)
⌉

{\displaystyle \lceil \log _{2}(b)\rceil }

 bits, where b is the number of bytes per data block. The tag contains the most significant bits of the address, which are checked against the current row (the row has been retrieved by index) to see if it is the one we need or another, irrelevant memory location that happened to have the same index bits as the one we want. The tag length in bits is address_length - index_length - block_offset_length.

text: Some authors refer to the block offset as simply the "offset"[7] or the "displacement".[8][9]

text: Example[edit]

text: The original Pentium 4 processor had a four-way set associative L1 data cache of 8 KiB in size, with 64-byte cache blocks. Hence, there are 8 KiB / 64 = 128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 25 = 32 different indices. There are 26 = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 21 + 5 + 6 = 32, and hence 21 bits for the tag field.

text: The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KiB in size, with 128-byte cache blocks. This implies 17 + 8 + 7 = 32, and hence 17 bits for the tag field.[7]

text: Flag bits[edit]

text: An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data.

text: On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times, such as when multi-master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in the local cache are now stale and should be marked invalid.

text: A data cache typically requires two flag bits per cache line –  a valid bit and a dirty bit. Having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory ("dirty"), meaning that the processor has written data to that line and the new value has not propagated all the way to main memory.

text: Associativity[edit]

text: The replacement policy decides where in the cache a copy of a particular entry of main memory will go. If the replacement policy is free to choose any entry in the cache to hold the copy, the cache is called fully associative. At the other extreme, if each entry in main memory can go in just one place in the cache, the cache is direct mapped. Many caches implement a compromise in which each entry in main memory can go to any one of N places in the cache, and are described as N-way set associative.[10] For example, the level-1 data cache in an AMD Athlon is two-way set associative, which means that any particular location in main memory can be cached in either of two locations in the level-1 data cache.

text: Choosing the right value of associativity involves a trade-off. If there are ten places to which the replacement policy could have mapped a memory location, then to check if that location is in the cache, ten cache entries must be searched. Checking more places takes more power and chip area, and potentially more time. On the other hand, caches with more associativity suffer fewer misses (see conflict misses, below), so that the CPU wastes less time reading from the slow main memory. The general guideline is that doubling the associativity, from direct mapped to two-way, or from two-way to four-way, has about the same effect on raising the hit rate as doubling the cache size. However, increasing associativity more than four does not improve hit rate as much,[11] and are generally done for other reasons (see virtual aliasing, below). Some CPUs can dynamically reduce the associativity of their caches in low-power states, which acts as a power-saving measure.[12]

text: In order of worse but simple to better but complex:

text:
Direct mapped cache –  good best-case time, but flaky in worst case
Two-way set associative cache
Two-way skewed associative cache[13]
Four-way set associative cache
Eight-way set associative cache, a common choice for later implementations
12-way set associative cache, similar to eight-way
Fully associative cache –  the best miss rates, but practical only for a small number of entries

tag: ul

text: Direct-mapped cache[edit]

text: In this cache organization, each location in main memory can go in only one entry in the cache. Therefore, a direct-mapped cache can also be called a "one-way set associative" cache. It does not have a replacement policy as such, since there is no choice of which cache entry's contents to evict. This means that if two locations map to the same entry, they may continually knock each other out. Although simpler, a direct-mapped cache needs to be much larger than an associative one to give comparable performance, and it is more unpredictable. Let x be block number in cache, y be block number of memory, and n be number of blocks in cache, then mapping is done with the help of the equation x = y mod n.

text: Two-way set associative cache[edit]

text: If each location in main memory can be cached in either of two locations in the cache, one logical question is: which one of the two? The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster. Also LRU is especially simple since only one bit needs to be stored for each pair.

text: Speculative execution[edit]

text: One of the advantages of a direct mapped cache is that it allows simple and fast speculation. Once the address has been computed, the one cache index which might have a copy of that location in memory is known. That cache entry can be read, and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address.

text: The idea of having the processor use the cached data before the tag match completes can be applied to associative caches as well. A subset of the tag, called a hint, can be used to pick just one of the possible cache entries mapping to the requested address. The entry selected by the hint can then be used in parallel with checking the full tag. The hint technique works best when used in the context of address translation, as explained below.

text: Two-way skewed associative cache[edit]

text: Other schemes have been suggested, such as the skewed cache,[13] where the index for way 0 is direct, as above, but the index for way 1 is formed with a hash function. A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside is extra latency from computing the hash function.[14] Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; LRU tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones.[15]

text: Pseudo-associative cache[edit]

text: A true set-associative cache tests all the possible ways simultaneously, using something like a content addressable memory. A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache.

text: In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than a direct-mapped cache, closer to the miss rate of a fully associative cache. [14]

text: Cache miss[edit]

text: A cache miss is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss.

text: Cache read misses from an instruction cache generally cause the largest delay, because the processor, or at least the thread of execution, has to wait (stall) until the instruction is fetched from main memory. Cache read misses from a data cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution. Cache write misses to a data cache generally cause the shortest delay, because the write can be queued and there are few limitations on the execution of subsequent instructions; the processor can continue until the queue is full. There is a more detailed introduction to the types of misses here.

text: Address translation[edit]

text: Most general purpose CPUs implement some form of virtual memory. To summarize, either each program running on the machine sees its own simplified address space, which contains code and data for that program only, or all programs run in a common virtual address space. A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write.

text: Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory. The portion of the processor that does this translation is known as the memory management unit (MMU). The fast path through the MMU can perform those translations stored in the translation lookaside buffer (TLB), which is a cache of mappings from the operating system's page table, segment table, or both.

text: For the purposes of the present discussion, there are three important features of address translation:

text:
Latency: The physical address is available from the MMU some time, perhaps a few cycles, after the virtual address is available from the address generator.
Aliasing: Multiple virtual addresses can map to a single physical address. Most processors guarantee that all updates to that single physical address will happen in program order. To deliver on that guarantee, the processor must ensure that only one copy of a physical address resides in the cache at any given time.
Granularity: The virtual address space is broken up into pages. For instance, a 4 GiB virtual address space might be cut up into 1,048,576 pages of 4 KiB size, each of which can be independently mapped. There may be multiple page sizes supported; see virtual memory for elaboration.

text: Some early virtual memory systems were very slow because they required an access to the page table (held in main memory) before every programmed access to main memory.[NB 1] With no caches, this effectively cut the speed of memory access in half. The first hardware cache used in a computer system was not actually a data or instruction cache, but rather a TLB.[17]

text: Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses:

text:
Physically indexed, physically tagged (PIPT) caches use the physical address for both the index and the tag. While this is simple and avoids problems with aliasing, it is also slow, as the physical address must be looked up (which could involve a TLB miss and access to main memory) before that address can be looked up in the cache.
Virtually indexed, virtually tagged (VIVT) caches use the virtual address for both the index and the tag. This caching scheme can result in much faster lookups, since the MMU does not need to be consulted first to determine the physical address for a given virtual address. However, VIVT suffers from aliasing problems, where several different virtual addresses may refer to the same physical address. The result is that such addresses would be cached separately despite referring to the same memory, causing coherency problems. Another problem is homonyms, where the same virtual address maps to several different physical addresses. It is not possible to distinguish these mappings merely by looking at the virtual index itself, though potential solutions include: flushing the cache after a context switch, forcing address spaces to be non-overlapping, tagging the virtual address with an address space ID (ASID), or using physical tags. Additionally, there is a problem that virtual-to-physical mappings can change, which would require flushing cache lines, as the VAs would no longer be valid.
Virtually indexed, physically tagged (VIPT) caches use the virtual address for the index and the physical address in the tag. The advantage over PIPT is lower latency, as the cache line can be looked up in parallel with the TLB translation, however the tag cannot be compared until the physical address is available. The advantage over VIVT is that since the tag has the physical address, the cache can detect homonyms. VIPT requires more tag bits, as the index bits no longer represent the same address.
Physically indexed, virtually tagged (PIVT) caches are often claimed in literature to be useless and non-existing.[18] However, the MIPS R6000 uses this cache type as the sole known implementation.[19] The R6000 is implemented in emitter-coupled logic, which is an extremely fast technology not suitable for large memories such as a TLB. The R6000 solves the issue by putting the TLB memory into a reserved part of the second-level cache having a tiny, high-speed TLB "slice" on chip. The cache is indexed by the physical address obtained from the TLB slice. However, since the TLB slice only translates those virtual address bits that are necessary to index the cache and does not use any tags, false cache hits may occur, which is solved by tagging with the virtual address.

text: The speed of this recurrence (the load latency) is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM.

text: But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed.

text: Caches have historically used both virtual and physical addresses for the cache tags, although virtual tagging is now uncommon. If the TLB lookup can finish before the cache RAM lookup, then the physical address is available in time for tag compare, and there is no need for virtual tagging. Large caches, then, tend to be physically tagged, and only small, very low latency caches are virtually tagged. In recent general-purpose CPUs, virtual tagging has been superseded by vhints, as described below.

text: Homonym and synonym problems[edit]

text: A cache that relies on virtual indexing and tagging becomes inconsistent after the same virtual address is mapped into different physical addresses (homonym), which can be solved by using physical address for tagging, or by storing the address space identifier in the cache line. However, the latter approach does not help against the synonym problem, in which several cache lines end up storing data for the same physical address. Writing to such locations may update only one location in the cache, leaving the others with inconsistent data. This issue may be solved by using non-overlapping memory layouts for different address spaces, or otherwise the cache (or a part of it) must be flushed when the mapping changes.[20]

text: Virtual tags and vhints[edit]

text: The great advantage of virtual tags is that, for associative caches, they allow the tag match to proceed before the virtual to physical translation is done. However, coherence probes and evictions present a physical address for action. The hardware must have some means of converting the physical addresses into a cache index, generally by storing physical tags as well as virtual tags. For comparison, a physically tagged cache does not need to keep virtual tags, which is simpler. When a virtual to physical mapping is deleted from the TLB, cache entries with those virtual addresses will have to be flushed somehow. Alternatively, if cache entries are allowed on pages not mapped by the TLB, then those entries will have to be flushed when the access rights on those pages are changed in the page table.

text: It is also possible for the operating system to ensure that no virtual aliases are simultaneously resident in the cache. The operating system makes this guarantee by enforcing page coloring, which is described below. Some early RISC processors (SPARC, RS/6000) took this approach. It has not been used recently, as the hardware cost of detecting and evicting virtual aliases has fallen and the software complexity and performance penalty of perfect page coloring has risen.

text: It can be useful to distinguish the two functions of tags in an associative cache: they are used to determine which way of the entry set to select, and they are used to determine if the cache hit or missed. The second function must always be correct, but it is permissible for the first function to guess, and get the wrong answer occasionally.

text: Some processors (e.g. early SPARCs) have caches with both virtual and physical tags. The virtual tags are used for way selection, and the physical tags are used for determining hit or miss. This kind of cache enjoys the latency advantage of a virtually tagged cache, and the simple software interface of a physically tagged cache. It bears the added cost of duplicated tags, however. Also, during miss processing, the alternate ways of the cache line indexed have to be probed for virtual aliases and any matches evicted.

text: The extra area (and some latency) can be mitigated by keeping virtual hints with each cache entry instead of virtual tags. These hints are a subset or hash of the virtual tag, and are used for selecting the way of the cache from which to get data and a physical tag. Like a virtually tagged cache, there may be a virtual hint match but physical tag mismatch, in which case the cache entry with the matching hint must be evicted so that cache accesses after the cache fill at this address will have just one hint match. Since virtual hints have fewer bits than virtual tags distinguishing them from one another, a virtually hinted cache suffers more conflict misses than a virtually tagged cache.

text: Perhaps the ultimate reduction of virtual hints can be found in the Pentium 4 (Willamette and Northwood cores). In these processors the virtual hint is effectively two bits, and the cache is four-way set associative. Effectively, the hardware maintains a simple permutation from virtual address to cache index, so that no content-addressable memory (CAM) is necessary to select the right one of the four ways fetched.

text: Page coloring[edit]

text: Large physically indexed caches (usually secondary caches) run into a problem: the operating system rather than the application controls which pages collide with one another in the cache. Differences in page allocation from one program run to the next lead to differences in the cache collision patterns, which can lead to very large differences in program performance. These differences can make it very difficult to get a consistent and repeatable timing for a benchmark run.

text: To understand the problem, consider a CPU with a 1 MiB physically indexed direct-mapped level-2 cache and 4 KiB virtual memory pages. Sequential physical pages map to sequential locations in the cache until after 256 pages the pattern wraps around. We can label each physical page with a color of 0–255 to denote where in the cache it can go. Locations within physical pages with different colors cannot conflict in the cache.

text: Programmers attempting to make maximum use of the cache may arrange their programs' access patterns so that only 1 MiB of data need be cached at any given time, thus avoiding capacity misses. But they should also ensure that the access patterns do not have conflict misses. One way to think about this problem is to divide up the virtual pages the program uses and assign them virtual colors in the same way as physical colors were assigned to physical pages before. Programmers can then arrange the access patterns of their code so that no two pages with the same virtual color are in use at the same time. There is a wide literature on such optimizations (e.g. loop nest optimization), largely coming from the High Performance Computing (HPC) community.

text: The snag is that while all the pages in use at any given moment may have different virtual colors, some may have the same physical colors. In fact, if the operating system assigns physical pages to virtual pages randomly and uniformly, it is extremely likely that some pages will have the same physical color, and then locations from those pages will collide in the cache (this is the birthday paradox).

text: The solution is to have the operating system attempt to assign different physical color pages to different virtual colors, a technique called page coloring. Although the actual mapping from virtual to physical color is irrelevant to system performance, odd mappings are difficult to keep track of and have little benefit, so most approaches to page coloring simply try to keep physical and virtual page colors the same.

text: If the operating system can guarantee that each physical page maps to only one virtual color, then there are no virtual aliases, and the processor can use virtually indexed caches with no need for extra virtual alias probes during miss handling. Alternatively, the OS can flush a page from the cache whenever it changes from one virtual color to another. As mentioned above, this approach was used for some early SPARC and RS/6000 designs.

text: Cache hierarchy in a modern processor[edit]

text: Modern processors have multiple interacting on-chip caches. The operation of a particular cache can be completely specified by the cache size, the cache block size, the number of blocks in a set, the cache set replacement policy, and the cache write policy (write-through or write-back).[7]

text: While all of the cache blocks in a particular cache are the same size and have the same associativity, typically the "lower-level" caches (called Level 1 cache) have a smaller number of blocks, smaller block size, and fewer blocks in a set, but have very short access times. "Higher-level" caches (i.e. Level 2 and above) have progressively larger numbers of blocks, larger block size, more blocks in a set, and relatively longer access times, but are still much faster than main memory.

text: Cache entry replacement policy is determined by a cache algorithm selected to be implemented by the processor designers. In some cases, multiple algorithms are provided for different kinds of work loads.

text: Specialized caches[edit]

text: Pipelined CPUs access memory from multiple points in the pipeline: instruction fetch, virtual-to-physical address translation, and data fetch (see classic RISC pipeline). The natural design is to use different physical caches for each of these points, so that no one physical resource has to be scheduled to service two points in the pipeline. Thus the pipeline naturally ends up with at least three separate caches (instruction, TLB, and data), each specialized to its particular role.

text: Victim cache[edit]

text: A victim cache is a cache used to hold blocks evicted from a CPU cache upon replacement. The victim cache lies between the main cache and its refill path, and only holds blocks that were evicted from the main cache. The victim cache is usually fully associative, and is intended to reduce the number of conflict misses. Many commonly used programs do not require an associative mapping for all the accesses. In fact, only a small fraction of the memory accesses of the program require high associativity. The victim cache exploits this property by providing high associativity to only these accesses. It was introduced by Norman Jouppi from DEC in 1990.[21]

text: Intel's Crystalwell[22] variant of its Haswell processors, equipped with Intel's Iris Pro GT3e embedded graphics and 128 MB of eDRAM, introduced an on-package Level 4 cache which serves as a victim cache to the processors's Level 3 cache.[23] In the Skylake processors the Level 4 cache no longer works as a victim cache.[24]

text: Trace cache[edit]

text: One of the more extreme examples of cache specialization is the trace cache (also known as execution trace cache) found in the Intel Pentium 4 microprocessors. A trace cache is a mechanism for increasing the instruction fetch bandwidth and decreasing power consumption (in the case of the Pentium 4) by storing traces of instructions that have already been fetched and decoded.[25]

text: A trace cache stores instructions either after they have been decoded, or as they are retired. Generally, instructions are added to trace caches in groups representing either individual basic blocks or dynamic instruction traces. The Pentium 4's trace cache stores micro-operations resulting from decoding x86 instructions, providing also the functionality of a micro-operation cache. Having this, the next time an instruction is needed, it does not have to be decoded into micro-ops again.[26]:63–68

text: Write Coalescing Cache (WCC)[edit]

text: Write Coalescing Cache[27] is a special cache that is part of L2 cache in AMD's Bulldozer microarchitecture. Stores from both L1D caches in the module go through the WCC, where they are buffered and coalesced. The WCC's task is reducing number of writes to the L2 cache.

text: Micro-operation (uop or μop) cache[edit]

text: A micro-operation cache (uop cache, μop cache or UC)[28] is a specialized cache that stores micro-operations of decoded instructions, as received directly from the instruction decoders or from the instruction cache. When an instruction needs to be decoded, the uop cache is checked for its decoded form which is re-used if cached; if it is not available, the instruction is decoded and then cached.

text: One of the early works describing uop cache as an alternative frontend for the Intel P6 processor family is the 2001 paper "Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA".[29] Later, Intel included uop caches in its Sandy Bridge processors and in successive microarchitectures like Ivy Bridge and Haswell.[26]:121–123[30] AMD implemented a uop cache in their Zen (microarchitecture).[31]

text: Fetching complete pre-decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed-length micro-operations, and simplifies the process of predicting, fetching, rotating and aligning fetched instructions. A uop cache effectively offloads the fetch and decode hardware, thus decreasing power consumption and improving the frontend supply of decoded micro-operations. The uop cache also increases performance by more consistently delivering decoded micro-operations to the backend and eliminating various bottlenecks in the CPU's fetch and decode logic.[29][30]

text: A uop cache has many similarities with a trace cache, although a uop cache is much simpler thus providing better power efficiency; this makes it better suited for implementations on battery-powered devices. The main disadvantage of the trace cache, leading to its power inefficiency, is the hardware complexity required for its heuristic deciding on caching and reusing dynamically created instruction traces.[32]

text: Multi-level caches[edit]

text: Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches. Multi-level caches generally operate by checking the fastest, level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If that smaller cache misses, the next fastest cache (level 2, L2) is checked, and so on, before accessing external memory.

text: As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. Price-sensitive designs used this to pull the entire cache hierarchy on-chip, but by the 2010s some of the highest-performance designs returned to having large off-chip caches, which is often implemented in eDRAM and mounted on a multi-chip module, as a fourth cache level.

text: The benefits of L3 and L4 caches depend on the application's access patterns. Examples of products incorporating L3 and L4 caches include the following:

text:
Alpha 21164 (1995) has 1 to 64 MB off-chip L3 cache.
IBM POWER4 (2001) has off-chip L3 caches of 32 MB per processor, shared among several processors.
Itanium 2 (2003) has a 6 MB unified level 3 (L3) cache on-die; the Itanium 2 (2003) MX 2 module incorporates two Itanium 2 processors along with a shared 64 MB L4 cache on a multi-chip module that was pin compatible with a Madison processor.
Intel's Xeon MP product codenamed "Tulsa" (2006) features 16 MB of on-die L3 cache shared between two processor cores.
AMD Phenom II (2008) has up to 6 MB on-die unified L3 cache.
Intel Core i7 (2008) has an 8 MB on-die unified L3 cache that is inclusive, shared by all cores.
Intel Haswell CPUs with integrated Intel Iris Pro Graphics have 128 MB of eDRAM acting essentially as an L4 cache.[33]

text: Finally, at the other end of the memory hierarchy, the CPU register file itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software—typically by a compiler, as it allocates registers to hold values retrieved from main memory, as an example loop nest optimization. However, with register renaming most compiler register assignments are reallocated dynamically by hardware at runtime into a register bank, allowing the CPU to break false data dependencies and thus easing pipeline hazards.

text: Register files sometimes also have hierarchy: The Cray-1 (circa 1976) had eight address "A" and eight scalar data "S" registers that were generally usable. There was also a set of 64 address "B" and 64 scalar data "T" registers that took longer to access, but were faster than main memory. The "B" and "T" registers were provided because the Cray-1 did not have a data cache. (The Cray-1 did, however, have an instruction cache.)

text: Multi-core chips[edit]

text: When considering a chip with multiple cores, there is a question of whether the caches should be shared or local to each core. Implementing shared cache undoubtedly introduces more wiring and complexity. But then, having one cache per chip, rather than core, greatly reduces the amount of space needed, and thus one can include a larger cache.

text: Typically, sharing the L1 cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single-core chip. However, for the highest-level cache, the last one called before accessing memory, having a global cache is desirable for several reasons, such as allowing a single core to use the whole cache, reducing data redundancy by making it possible for different processes or threads to share cached data, and reducing the complexity of utilized cache coherency protocols.[34] For example, an eight-core chip with three levels may include an L1 cache for each core, one intermediate L2 cache for each pair of cores, and one L3 cache shared between all cores.

text: Shared highest-level cache, which is called before accessing memory, is usually referred to as the last level cache (LLC). Additional techniques are used for increasing the level of parallelism when LLC is shared between multiple cores, including slicing it into multiple pieces which are addressing certain ranges of memory addresses, and can be accessed independently.[35]

text: Separate versus unified[edit]

text: In a separate cache structure, instructions and data are cached separately, meaning that a cache line is used to cache either instructions or data, but not both; various benefits have been demonstrated with separate data and instruction translation lookaside buffers.[36] In a unified structure, this constraint is not present, and cache lines can be used to cache both instructions and data.

text: Exclusive versus inclusive[edit]

text: Multi-level caches introduce new design decisions. For instance, in some processors, all data in the L1 cache must also be somewhere in the L2 cache. These caches are called strictly inclusive. Other processors (like the AMD Athlon) have exclusive caches: data is guaranteed to be in at most one of the L1 and L2 caches, never in both. Still other processors (like the Intel Pentium II, III, and 4) do not require that data in the L1 cache also reside in the L2 cache, although it may often do so. There is no universally accepted name for this intermediate policy.[37][38]

text: The advantage of exclusive caches is that they store more data. This advantage is larger when the exclusive L1 cache is comparable to the L2 cache, and diminishes if the L2 cache is many times larger than the L1 cache. When the L1 misses and the L2 hits on an access, the hitting cache line in the L2 is exchanged with a line in the L1. This exchange is quite a bit more work than just copying a line from L2 to L1, which is what an inclusive cache does.[38]

text: One advantage of strictly inclusive caches is that when external devices or other processors in a multiprocessor system wish to remove a cache line from the processor, they need only have the processor check the L2 cache. In cache hierarchies which do not enforce inclusion, the L1 cache must be checked as well. As a drawback, there is a correlation between the associativities of L1 and L2 caches: if the L2 cache does not have at least as many ways as all L1 caches together, the effective associativity of the L1 caches is restricted. Another disadvantage of inclusive cache is that whenever there is an eviction in L2 cache, the (possibly) corresponding lines in L1 also have to get evicted in order to maintain inclusiveness. This is quite a bit of work, and would result in a higher L1 miss rate.[38]

text: Another advantage of inclusive caches is that the larger cache can use larger cache lines, which reduces the size of the secondary cache tags. (Exclusive caches require both caches to have the same size cache lines, so that cache lines can be swapped on a L1 miss, L2 hit.) If the secondary cache is an order of magnitude larger than the primary, and the cache data is an order of magnitude larger than the cache tags, this tag area saved can be comparable to the incremental area needed to store the L1 cache data in the L2.[39]

text: Example: the K8[edit]

text: To illustrate both specialization and multi-level caching, here is the cache hierarchy of the K8 core in the AMD Athlon 64 CPU.[40]

text: The K8 has four specialized caches: an instruction cache, an instruction TLB, a data TLB, and a data cache. Each of these caches is specialized:

text:
The instruction cache keeps copies of 64-byte lines of memory, and fetches 16 bytes each cycle. Each byte in this cache is stored in ten bits rather than eight, with the extra bits marking the boundaries of instructions (this is an example of predecoding). The cache has only parity protection rather than ECC, because parity is smaller and any damaged data can be replaced by fresh data fetched from memory (which always has an up-to-date copy of instructions).
The instruction TLB keeps copies of page table entries (PTEs). Each cycle's instruction fetch has its virtual address translated through this TLB into a physical address. Each entry is either four or eight bytes in memory. Because the K8 has a variable page size, each of the TLBs is split into two sections, one to keep PTEs that map 4 KB pages, and one to keep PTEs that map 4 MB or 2 MB pages. The split allows the fully associative match circuitry in each section to be simpler. The operating system maps different sections of the virtual address space with different size PTEs.
The data TLB has two copies which keep identical entries. The two copies allow two data accesses per cycle to translate virtual addresses to physical addresses. Like the instruction TLB, this TLB is split into two kinds of entries.
The data cache keeps copies of 64-byte lines of memory. It is split into 8 banks (each storing 8 KB of data), and can fetch two 8-byte data each cycle so long as those data are in different banks. There are two copies of the tags, because each 64-byte line is spread among all eight banks. Each tag copy handles one of the two accesses per cycle.

text: The K8 also has multiple-level caches. There are second-level instruction and data TLBs, which store only PTEs mapping 4 KB. Both instruction and data caches, and the various TLBs, can fill from the large unified L2 cache. This cache is exclusive to both the L1 instruction and data caches, which means that any 8-byte line can only be in one of the L1 instruction cache, the L1 data cache, or the L2 cache. It is, however, possible for a line in the data cache to have a PTE which is also in one of the TLBs—the operating system is responsible for keeping the TLBs coherent by flushing portions of them when the page tables in memory are updated.

text: The K8 also caches information that is never stored in memory—prediction information. These caches are not shown in the above diagram. As is usual for this class of CPU, the K8 has fairly complex branch prediction, with tables that help predict whether branches are taken and other tables which predict the targets of branches and jumps. Some of this information is associated with instructions, in both the level 1 instruction cache and the unified secondary cache.

text: The K8 uses an interesting trick to store prediction information with instructions in the secondary cache. Lines in the secondary cache are protected from accidental data corruption (e.g. by an alpha particle strike) by either ECC or parity, depending on whether those lines were evicted from the data or instruction primary caches. Since the parity code takes fewer bits than the ECC code, lines from the instruction cache have a few spare bits. These bits are used to cache branch prediction information associated with those instructions. The net result is that the branch predictor has a larger effective history table, and so has better accuracy.

text: More hierarchies[edit]

text: Other processors have other kinds of predictors (e.g. the store-to-load bypass predictor in the DEC Alpha 21264), and various specialized predictors are likely to flourish in future processors.

text: These predictors are caches in that they store information that is costly to compute. Some of the terminology used when discussing predictors is the same as that for caches (one speaks of a hit in a branch predictor), but predictors are not generally thought of as part of the cache hierarchy.

text: The K8 keeps the instruction and data caches coherent in hardware, which means that a store into an instruction closely following the store instruction will change that following instruction. Other processors, like those in the Alpha and MIPS family, have relied on software to keep the instruction cache coherent. Stores are not guaranteed to show up in the instruction stream until a program calls an operating system facility to ensure coherency.

text: Tag RAM[edit]

text: In computer engineering, a tag RAM is used to specify which of the possible memory locations is currently stored in a CPU cache.[41][42] For a simple, direct-mapped design fast SRAM can be used. Higher associative caches usually employ content-addressable memory.

text: Implementation[edit]

text: Cache reads are the most common CPU operation that takes more than a single cycle. Program execution time tends to be very sensitive to the latency of a level-1 data cache hit. A great deal of design effort, and often power and silicon area are expended making the caches as fast as possible.

text: The simplest cache is a virtually indexed direct-mapped cache. The virtual address is calculated with an adder, the relevant portion of the address extracted and used to index an SRAM, which returns the loaded data. The data is byte aligned in a byte shifter, and from there is bypassed to the next operation. There is no need for any tag checking in the inner loop –  in fact, the tags need not even be read. Later in the pipeline, but before the load instruction is retired, the tag for the loaded data must be read, and checked against the virtual address to make sure there was a cache hit. On a miss, the cache is updated with the requested cache line and the pipeline is restarted.

text: An associative cache is more complicated, because some form of tag must be read to determine which entry of the cache to select. An N-way set-associative level-1 cache usually reads all N possible tags and N data in parallel, and then chooses the data associated with the matching tag. Level-2 caches sometimes save power by reading the tags first, so that only one data element is read from the data SRAM.

text: The diagram to the right is intended to clarify the manner in which the various fields of the address are used. Address bit 31 is most significant, bit 0 is least significant. The diagram shows the SRAMs, indexing, and multiplexing for a 4 KB, 2-way set-associative, virtually indexed and virtually tagged cache with 64 byte (B) lines, a 32-bit read width and 32-bit virtual address.

text: Because the cache is 4 KB and has 64 B lines, there are just 64 lines in the cache, and we read two at a time from a Tag SRAM which has 32 rows, each with a pair of 21 bit tags. Although any function of virtual address bits 31 through 6 could be used to index the tag and data SRAMs, it is simplest to use the least significant bits.

text: Similarly, because the cache is 4 KB and has a 4 B read path, and reads two ways for each access, the Data SRAM is 512 rows by 8 bytes wide.

text: A more modern cache might be 16 KB, 4-way set-associative, virtually indexed, virtually hinted, and physically tagged, with 32 B lines, 32-bit read width and 36-bit physical addresses. The read path recurrence for such a cache looks very similar to the path above. Instead of tags, vhints are read, and matched against a subset of the virtual address. Later on in the pipeline, the virtual address is translated into a physical address by the TLB, and the physical tag is read (just one, as the vhint supplies which way of the cache to read). Finally the physical address is compared to the physical tag to determine if a hit has occurred.

text: Some SPARC designs have improved the speed of their L1 caches by a few gate delays by collapsing the virtual address adder into the SRAM decoders. See Sum addressed decoder.

text: History[edit]

text: The early history of cache technology is closely tied to the invention and use of virtual memory.[citation needed] Because of scarcity and cost of semi-conductor memories, early mainframe computers in the 1960s used a complex hierarchy of physical memory, mapped onto a flat virtual memory space used by programs. The memory technologies would span semi-conductor, magnetic core, drum and disc. Virtual memory seen and used by programs would be flat and caching would be used to fetch data and instructions into the fastest memory ahead of processor access. Extensive studies were done to optimize the cache sizes. Optimal values were found to depend greatly on the programming language used with Algol needing the smallest and Fortran and Cobol needing the largest cache sizes.[disputed – discuss]

text: In the early days of microcomputer technology, memory access was only slightly slower than register access. But since the 1980s[43] the performance gap between processor and memory has been growing. Microprocessors have advanced much faster than memory, especially in terms of their operating frequency, so memory became a performance bottleneck. While it was technically possible to have all the main memory as fast as the CPU, a more economically viable path has been taken: use plenty of low-speed memory, but also introduce a small high-speed cache memory to alleviate the performance gap. This provided an order of magnitude more capacity—for the same price—with only a slightly reduced combined performance.

text: First TLB implementations[edit]

text: The first documented uses of a TLB were on the GE 645[44] and the IBM 360/67,[45] both of which used an associative memory as a TLB.

text: First data cache[edit]

text: The first documented use of a data cache was on the IBM System/360 Model 85.[46]

text: In 68k microprocessors[edit]

text: The 68010, released in 1982, has a "loop mode" which can be considered a tiny and special-case instruction cache that accelerates loops that consist of only two instructions. The 68020, released in 1984, replaced that with a typical instruction cache of 256 bytes, being the first 68k series processor to feature true on-chip cache memory.

text: The 68030, released in 1987, is basically a 68020 core with an additional 256-byte data cache, a process shrink, and added burst mode for the caches. The 68040, released in 1990, has split instruction and data caches of four kilobytes each. The 68060, released in 1994, has the following: 8 KB data cache (four-way associative), 8 KB instruction cache (four-way associative), 96-byte FIFO instruction buffer, 256-entry branch cache, and 64-entry address translation cache MMU buffer (four-way associative).

text: In x86 microprocessors[edit]

text: As the x86 microprocessors reached clock rates of 20 MHz and above in the 386, small amounts of fast cache memory began to be featured in systems to improve performance. This was because the DRAM used for main memory had significant latency, up to 120 ns, as well as refresh cycles. The cache was constructed from more expensive, but significantly faster, SRAM memory cells, which at the time had latencies around 10 ns. The early caches were external to the processor and typically located on the motherboard in the form of eight or nine DIP devices placed in sockets to enable the cache as an optional extra or upgrade feature.

text: Some versions of the Intel 386 processor could support 16 to 64 KB of external cache.

text: With the 486 processor, an 8 KB cache was integrated directly into the CPU die. This cache was termed Level 1 or L1 cache to differentiate it from the slower on-motherboard, or Level 2 (L2) cache. These on-motherboard caches were much larger, with the most common size being 256 KB. The popularity of on-motherboard cache continued through the Pentium MMX era but was made obsolete by the introduction of SDRAM and the growing disparity between bus clock rates and CPU clock rates, which caused on-motherboard cache to be only slightly faster than main memory.

text: The next development in cache implementation in the x86 microprocessors began with the Pentium Pro, which brought the secondary cache onto the same package as the microprocessor, clocked at the same frequency as the microprocessor.

text: On-motherboard caches enjoyed prolonged popularity thanks to the AMD K6-2 and AMD K6-III processors that still used the venerable Socket 7, which was previously used by Intel with on-motherboard caches. K6-III included 256 KB on-die L2 cache and took advantage of the on-board cache as a third level cache, named L3 (motherboards with up to 2 MB of on-board cache were produced). After the Socket 7 became obsolete, on-motherboard cache disappeared from the x86 systems.

text: The three-level caches were used again first with the introduction of multiple processor cores, where the L3 cache was added to the CPU die. It became common for the total cache sizes to be increasingly larger in newer processor generations, and recently (as of 2011) it is not uncommon to find Level 3 cache sizes of tens of megabytes.[47]

text: Intel introduced a Level 4 on-package cache with the Haswell microarchitecture. Crystalwell[22] Haswell CPUs, equipped with the GT3e variant of Intel's integrated Iris Pro graphics, effectively feature 128 MB of embedded DRAM (eDRAM) on the same package. This L4 cache is shared dynamically between the on-die GPU and CPU, and serves as a victim cache to the CPU's L3 cache.[23]

text: Current research[edit]

text: Early cache designs focused entirely on the direct cost of cache and RAM and average execution speed. More recent cache designs also consider energy efficiency,[48] fault tolerance, and other goals.[49] Researchers have also explored use of emerging memory technologies such as eDRAM (embedded DRAM) and NVRAM (non-volatile RAM) for designing caches.[50]

text: There are several tools available to computer architects to help explore tradeoffs between the cache cycle time, energy, and area. These tools include the open-source CACTI cache simulator[51] and the open-source SimpleScalar instruction set simulator. Modeling of 2D and 3D SRAM, eDRAM, STT-RAM, ReRAM and PCM caches can be done using the DESTINY tool.[52]

text: Multi-ported cache[edit]

text: A multi-ported cache is a cache which can serve more than one request at a time. When accessing a traditional cache we normally use a single memory address, whereas in a multi-ported cache we may request N addresses at a time –  where N is the number of ports that connected through the processor and the cache. The benefit of this is that a pipelined processor may access memory from different phases in its pipeline. Another benefit is that it allows the concept of super-scalar processors through different cache levels.


document_title: Dr. Nick

question_text: where did dr nick go to medical school

question_tokens: where did dr nick go to medical school

root

text: Dr. Nick

text: Role in The Simpsons[edit]

text: Dr. Nick has a medical degree from "Hollywood Upstairs Medical College", in the 1970s, where he apparently spent much of his time using his ability to acquire prescription drugs to impress women.[1] Thus far, none of the patients he has swindled, maimed, or given useless or dangerous medical advice seems to have sued him—although a few have come after him in person. For example, in "Homer's Triple Bypass", a large angry man grabs him, and Riviera says "Well if it isn't my old friend Mr. McGregg—with a leg for an arm and an arm for a leg"; the man literally has an arm where a leg should be and a leg where an arm should be, and it is implied that this is Riviera's fault.[1] Riviera is a stereotype of shady doctors who perform medical procedures for money with little or no regard for medical ethics, or their patients' well-being. His motto is, You've tried the best, now try the rest! In "The Girl Who Slept Too Little", he is seen digging up corpses in the graveyard for body parts, presumably to use in operations on patients. In the same episode he tells Lisa "you have a check-up on Thursday!", to which she replies "We don't go to you anymore, we have a better doctor!" and receives a congratulation from him. In "Treehouse of Horror IX", he injects himself with anesthetic after punching Homer in the face in order to knock him out before performing a hair transplant on him, using a pizza cutter.

tag: p

text: In the episode "Much Apu About Nothing", he is seen taking a citizenship test, implying that prior to this he was not a citizen of the United States. Though his origin remains unconfirmed, Dr Nick has a notable Argentine accent in the Spanish-language dubs. In the episode "Margical History Tour", the sequence set in 18th-century Vienna has Dr. Nick saying "Guten Tag, everybody!"

text: The degrees in his office read "Mayo Clinic Correspondence School", "Club Med School", "Female Body Inspector", and "I went to medical school for four years and all I got was this lousy diploma".[2] He is a member of Sigma Chi fraternity. He frequently appears on infomercials, pitching all sorts of bizarre medical offers or endorsing dubious devices, and has often turned his operations into TV spectacles. He is also shown as an inventor/huckster (in the style of Ron Popeil) on the television show I Can't Believe They Invented It!, with products such as the "Juice Loosener" in "Marge in Chains", an inefficient juicer made in Japan which ultimately causes an influenza epidemic in Springfield (due to one of the workers at the factory having the disease, but still going to work, thus spreading his germs through the packaging).

text: Dr. Nick has operated on the Simpson family a couple of times when they cannot afford their regular doctor, Dr. Hibbert, notably when Homer needed a heart bypass. Lisa Simpson attended the live audience for the operation and saved the day by guiding the obviously clueless Dr. Riviera through the operation.[1] He also worked with Dr. Hibbert as an anesthesiologist during Bart's appendectomy (in 'Round Springfield) but was of little help as he accidentally anesthetized himself instead. It is revealed in the episode "Homer's Triple Bypass" that his phone number is 1-600-DOCTORB, explaining that: "The B is for Bargain!".[1] His catchphrase is "Hi everybody!", except in The Simpsons Movie, in which he was seemingly killed with a large shard of glass, saying, "Bye, everybody... ugh." However, he has survived and made a few appearances since.

text: Character[edit]

text: The design of Dr. Nick is modeled physically on Gábor Csupó, the co-founder of Klasky Csupo animation studios (which animated the series for its first three seasons and The Tracey Ullman Show shorts).[3] The animators mistakenly believed that Hank Azaria was impersonating Csupó, when in fact he was doing a bad impression of Ricky Ricardo from the TV series I Love Lucy.[4]

text: In The Simpsons Movie, Riviera is impaled by a large shard of glass that breaks and falls off the enormous dome covering Springfield, saying "Bye, everybody!" before he faints. Executive producers James L. Brooks and Al Jean confirmed that the character was not dead, but he just fainted[citation needed], and he would be "brought back to life à la Dr. Marvin Monroe".[5] Riviera is seen alive and well in further episodes after the movie.

text: Reception[edit]

text: IGN placed Dr. Nick 23rd on their list of the "Top 25 Simpsons Peripheral Characters".[6] The character was listed in Entertainment Weekly's "30 Great TV Doctors and Nurses" and in Philadelphia Magazine's "10 Best Doctors on Television".[7][8] In a tongue-in-cheek analysis, the Canadian Medical Association Journal compared the services of Riviera and Dr. Hibbert. It concludes that Riviera is a better role model for physicians, whereas Hibbert is a paternalistic and wasteful physician, unlike Riviera, who strives to cut costs and does his best to avoid the coroner, disproving Marge Simpson's claim that he is not a doctor at all.[9]


document_title: MS Harmony of the Seas

question_text: when did harmony of the seas set sail

question_tokens: when did harmony of the seas set sail

text: MS Harmony of the Seas

text: History[edit]

text: The success of the first two Oasis-class ships led Royal Caribbean Cruises to order a third ship of the type in December 2012.[1] Harmony of the Seas was floated out on 19 June 2015, began her first sea trials on 10 March 2016,[15] and was delivered to Royal Caribbean on 12 May 2016.[5][16] After a construction time of 32 months, the ship first set sail on 15 May 2016 from the STX France docks in Saint-Nazaire, viewed by some 70,000 people.[17] Her first destination was Southampton, England, although her home port was Barcelona until 23 October 2016 when she crossed the Atlantic.[18]

text: Harmony of the Seas took two short "preview cruises", three nights to Cherbourg and four nights to Rotterdam, after reaching port in Southampton on 17 May.[19] During these voyages, passengers complained of ongoing construction, a lack of hot water, unopened attractions, excessive waits at restaurants, and other issues.[20] The ship's maiden voyage departed from Southampton on 29 May and arrived at its summer home port of Barcelona on 5 June. According to passengers on this cruise, construction had finished and the ship was ready to sail.[21]

text: On 10 November 2016, the vessel was officially christened by her godmother, Miami-Dade County teacher Brittany Affolter.[22]

text: Routing[edit]

text: For the inaugural season, Harmony of the Seas offered seven-night western Mediterranean cruises originating from Barcelona and Civitavecchia.[23]

text: Accommodations[edit]

text: Harmony of the Seas has 2,747 staterooms, with a wide variety of types, to accommodate (at double occupancy) 5,479 guests[24] ranging from small interior rooms to larger rooms and suites, some of which are fitted with wall-mounted 80-inch (200 cm) screens, covering nearly the floor to ceiling,[25] that show the ship's environment as if through a window, named 'virtual balconies'. These screens were first fitted on the Quantum class of cruise ships.[26] A full 43 categories of stateroom types are offered, starting at a size of 180 square feet (17 m2); several types of suites are available, including the new "Royal Class" suites.[27]

text: Amenities[edit]

text: As the third member of the Oasis class, Harmony of the Seas is very similar to her two sister ships. However, there are some design changes and extra amenities, most noticeably the "Ultimate Abyss" dry slide at the stern of the ship and the "Perfect Storm" water slides.[28] Harmony of the Seas is the second Royal Caribbean ship to feature water slides, after Liberty of the Seas underwent a refurbishment in January 2016 that added water slides and Splashaway Bay. The ship is divided into seven neighborhoods, including Central Park and Boardwalk, like her Oasis-class sisters.[29] Amenities include:[30]

text:
"Vitality" Spa and fitness center
"Splashaway Bay" water play area for young children
"Perfect Storm" water slide complex, featuring three slides
"Ultimate Abyss" dry slide complex, with two ten-story tall enclosed slides[31]
23 swimming pools and 10 hot tubs, including two hot tubs cantilevered over the edge of the ship[16]
2 Flowrider surf simulators[32]
"Casino Royale" casino with a full selection of slot machines and table games
"Puzzle Break: Escape the Rubicon" escape room game designed by Seattle-based Puzzle Break and ShowFX[33]
20 dining venues,[34] including "Wonderland" molecular gastronomy restaurant[32]
11,252 works of art[32]
Studio B Ice Rink
The Aqua Theatre, an open-air stage which hosts diving, aerial and acrobatics shows
The Bionic Bar, where drinks are made solely by two robotic arms[35]
The Royal Theatre, a 1,400 seat venue for Broadway-style shows such as Grease, Royal Caribbean's original show Columbus, and 3D movies[36]
DreamWorks Experience, with characters from Shrek, Kung Fu Panda, etc.
Two rock climbing walls[35]
Full-size basketball court, miniature golf course and ping pong tables[35]
Zip line[35]
Adventure Ocean programs for children and youth; also Royal Babies and Royal Tots programs[16]
"Voom" high-speed Internet[37]
Optional RFID enabled wristbands (WOWbands) which will provide the same functions as the SeaPass cards[37]
Promenade shopping mall featuring jewelry, fashion and accessories
Rising Tides Bar, a bar platform that raises and lowers three floors between the Promenade level and the Central Park level
Carousel, Johnny Rockets, Starbucks, snacks and entertainment on the Boardwalk area
Central Park, an open air garden path with food and shops

text: Technology[edit]

text: Harmony of the Seas is 20% more energy efficient than her sister ships Oasis of the Seas and Allure of the Seas. Small air bubbles from the keel reduce drag and thus fuel consumption by 7-8%, and a smooth hull surface further reduces resistance. The bubble system also reduces propeller noise, and is used on Celebrity Reflection and Quantum of the Seas. LED and fluorescent lamps replace incandescent light bulbs, reducing power consumption and need for air conditioning. The engine system uses a waste heat recovery system, and drives three Azipod propellers.[38][39][40]

text: Incidents[edit]

text: On 13 September 2016, one employee was killed and four were injured when a life boat broke loose and dropped from the fifth deck during a security drill.[41][42]


document_title: Sun sign astrology

question_text: the movement of earth around the sun is called answers.com

text: Sun sign astrology

text: History[edit]

text: Although William Lilly in the 17th century was the first newspaper astrologer, sun sign astrology was not invented until 1930. The astrologer R. H. Naylor was claimed by his newspaper to have predicted the crash of the R101 airship. This led to pressure on Naylor to come up with a simplified system of astrology suitable for a newspaper column. After some experimentation, Naylor decided on sun signs.[citation needed]

text: Sun signs[edit]

text: The following table[1] shows the zodiac names in Latin, with their English translation and the individuals' names. It also shows the element and quality associated with each sign. The starting and ending dates of the sun sign are approximate, as they may differ from one year to another (by a day or so), due to the fact that the earth's orbit around the sun is not synchronous with earth's rotation (one year does not comprehend a whole number of days).[2][3] The exact date and time of sign entrance/exit (which is corresponded to the 12 "mid-climates" within Chinese lunisolar calendar) must be obtained with appropriate software or with the help of an ephemeris.

text:
Symbol
Sign names
Individuals' names
English name
Element
Quality
(Modality)

Polarity
Associated
Celestial Body

period of Sun sign with approx. dates
1/2 days variation[2][3]

Capricorn
Capricorn
The Mountain Sea-Goat
Earth
Cardinal
Negative
Saturn
Winter Solstice (December 22) – the day before Great Cold

Aquarius
Aquarian
The Water-Bearer
Air
Fixed
Positive
Uranus (Saturn)
Great Cold (January 20) – the day before Vernal Showers

Pisces
Piscean
The Fish
Water
Mutable
Negative
Neptune (Jupiter)
Vernal Showers (February 19) – the day before Vernal Equinox

Aries
Arian/Arien
The Ram
Fire
Cardinal
Positive
Mars (Pluto)
Vernal Equinox (March 21) – the day before Corn Rain

Taurus
Taurean
The Bull
Earth
Fixed
Negative
Venus/Earth
Corn Rain (April 20 – the day before Corn Forms

Gemini
Geminian
The Twins
Air
Mutable
Positive
Mercury
Corn Forms (May 21)[4] – the day before Summer Solstice

Cancer
Cancerian
The Crab
Water
Cardinal
Negative
Moon
Summer Solstice (June 21)[4] – the day before Great Heat

Leo
Leo
The Lion
Fire
Fixed
Positive
Sun
Great Heat (July 24) – the day before End of Heat

Virgo
Virgin
The Maiden
Earth
Mutable
Negative
Mercury
End of Heat (August 23) – the day before Autumnal Equinox

Libra
Libran
The Scales
Air
Cardinal
Positive
Venus
Autumnal Equinox (September 23)[4] – the day before First Frost

Scorpio
Scorpio
The Scorpion
Water
Fixed
Negative
Pluto (Mars)
First Frost (October 23) – the day before Light Snow

Sagittarius
Sagittarian
The Archer
Fire
Mutable
Positive
Jupiter
Light Snow (November 23) – the day before Winter Solstice

tag: table

text: Traditional planets in brackets


document_title: Shooter (TV series)

question_text: how many episodes in season 3 of shooter

text: Shooter (TV series)

text: Cast and characters[edit]

text: Main[edit]

text:
Ryan Phillippe as Bob Lee Swagger, a highly trained Force Recon Marine and MARSOC CSO Scout Sniper[11]
Shantel VanSanten as Julie Swagger, Bob Lee's wife[12]
Cynthia Addai-Robinson as Nadine Memphis,[13] an FBI agent investigating Swagger
Eddie McClintock as Jack Payne,[14] a figure involved in the conspiracy against Swagger (season 1; guest, season 3)
Omar Epps as Isaac Johnson, a Secret Service Agent who is also a former Force Recon Marine captain, MARSOC CSO, and commanding officer of Swagger[15]
Josh Stewart as Solotov, a Chechen master sniper with whom Bob Lee has tangled before (seasons 2–3)
Jesse Bradford as Harris Downey, a D.C. staffer who was once involved with Nadine (recurring, season 2; main, season 3)
Gerald McRaney as Red Bama Sr., owner of Bama Cattle and an Undersecretary in the Department of Agriculture (season 3)

text: Recurring[edit]

text:
David Andrews as Sam Vincent, Bob Lee's close friend and lawyer.
David Marciano as Howard Utey, Nadine Memphis' superior at the FBI (season 1)
Lexy Kolker as Mary Swagger, Bob Lee's and Julie's daughter
Tom Sizemore as Hugh Meachum, a CIA black ops operative with mysterious motives (season 1)
Rob Brown as Donny Fenn, Swagger's best friend and spotter who was killed by Solotov (seasons 1–2)
Sean Cameron Michael as Grigory Krukov, a Russian FSB agent (season 1)[16]
Delaina Mitchell as Anna Wallingford, Julie's married sister and Mary's aunt
Matt Shallenberger as John Wheeler, a mysterious and deadly Atlas operative (seasons 1, 3)
Desmond Harrington as Lon Scott, a CEO of Anhur Dynamics (season 1)
Beverly D'Angelo as Patricia Gregson, a former National Security Advisor[17]
Jerry Ferrara as Kirk Zehnder, a former marine who always detects a conspiracy and is part of the core team of Bob Lee Swagger (season 2)
Todd Lowe as Colin Dobbs, a former marine in Swagger's unit, now living in Texas an hour from the Swagger Ranch (season 2)
Patrick Sabongui as Yusuf Ali, a core member of Swagger's original Marine team (season 2)
Jaina Lee Ortiz as Angela Tio, a Marine and part of Bob Lee’s former unit (season 2)
John Marshall Jones as Sheriff Brown, the local law enforcement in Bob Lee's hometown and a long-time friend (season 2–3)
Harry Hamlin as Sen. Addison Hayes, a mysterious and powerful mastermind whose agenda will collide with Swagger (seasons 2–3)[18]
Troy Garity as Jeffrey Denning, a seasoned investigative journalist who cares deeply about justice being served (season 2)
Derek Phillips as Earl Swagger, Bob Lee's father, a Vietnam verteran who was sheriff in Bob Lee's hometown before he was killed 30 years ago (season 3)
Eric Ladin as Red Bama Jr., Red Sr's screw-up of a son who desperately wants his father's respect and confidence (season 3)
Felisha Terrell as Carlita Cruise, a former Atlas operative who is forced into working with Isaac and Nadine in order to preserve her own life (season 3)

text: Production[edit]

text: On July 6, 2016, while filming a scene at Agua Dulce Airpark, actor Tom Sizemore accidentally ran over a stuntman. Sizemore was supposed to enter the Cadillac Escalade and stay there until the scene ended, but the stunt coordinator told him to pull out, not realizing that the stuntman was behind him.[19]

text: On July 26, 2017, the second-season episode order was cut back from the planned ten episodes to the eight episodes already filmed after Ryan Phillippe broke his leg on July 16, 2017, in an incident unrelated to the series.[20]

text: Episodes[edit]

text: SeasonEpisodesOriginally airedFirst airedLast aired110November 15, 2016 (2016-11-15)January 17, 2017 (2017-01-17)28July 18, 2017 (2017-07-18)September 5, 2017 (2017-09-05)313June 21, 2018 (2018-06-21)September 13, 2018 (2018-09-13)

text: Season 1 (2016–17)[edit]

text:
No.overallNo. inseasonTitleDirected byWritten byOriginal air dateU.S. viewers(millions)11"Point of Impact"Simon Cellan JonesStory by : John Hlavin Teleplay by : John Hlavin & Jonathan LemkinNovember 15, 2016 (2016-11-15)1.44[21]
Bob Lee Swagger, a retired Marine Corps sniper, is approached by Isaac, his former captain, now in the US Secret Service, to do some security work before the President's visit to Seattle. His job is to scout the venues for possible sniper nests due to credible threat. However, he is unable to prevent the shot from being taken; the visiting Ukrainian president is killed and Bob Lee is the fall guy. Nadine, a disgraced FBI agent, arrests him.
22"Exfil"Simon Cellan JonesJohn HlavinNovember 22, 2016 (2016-11-22)1.25[22]
Awaiting arraignment, Bob Lee has to stay alive in federal prison, while the conspirators are trying to get him killed. During one of those botched attempts, Bob Lee manages to escape. He vows to do what he does best: hunt.
33"Musa Qala"Roxann DawsonAdam E. FierroNovember 29, 2016 (2016-11-29)1.67[23]
Since Bob Lee is out in the world, he's the subject of a manhunt. He is able to tell his wife that Isaac is part of the conspiracy and later gets help from a friend at the VA to fake his own death and become a ghost. He trusts Nadine with this secret.
44"Overwatch"Simon Cellan JonesT.J. Brady & Rasheed NewsonDecember 6, 2016 (2016-12-06)1.36[24]
In flashbacks, Isaac is saved by Bob Lee in Afghanistan in a plot to snatch a warlord for the CIA. Meanwhile, the conspirators try to silence Nadine, who started asking the wrong questions, though Bob Lee is just in time to save her.
55"Recon by Fire"Adam DavidsonDara ResnikDecember 13, 2016 (2016-12-13)1.30[25]
Bob Lee finds the original bullet used in the assassination and traces it back to a fringe militia. Even though they aren't the source for the bullet, they are preparing for something nefarious and Bob Lee stops them.
66"Killing Zone"Simon Cellan JonesMatt BosackDecember 20, 2016 (2016-12-20)1.53[26]
Bob Lee follows the breadcrumbs the bullet left to his former instructor, O'Brien. He tells Bob Lee to find the "black kings", one of only four sniper rifles capable of making the shot. He gives Bob Lee his own black king after they both deal with a clandestine outfit the conspirators send on their path called "Annex B". Nadine is finally able to convince her boss at the FBI some things aren't adding up.
77"Danger Close"Christoph SchreweTim TalbottDecember 27, 2016 (2016-12-27)1.63[27]
Bob Lee crosses the country to find the shooter while Julie deals with a family betrayal. Meanwhile, Nadine contacts a Ukrainian reporter who can explain the conspiracy. Also, Isaac questions his allegiance.
88"Red on Red"Kevin BrayMatthew NewmanJanuary 3, 2017 (2017-01-03)1.43[28]
Bob Lee and Nadine weave a plan to secure the evidence that could expose the conspiracy. Meanwhile, Isaac gropes for an exit strategy, Payne tries to flee, and Julie and Mary face grave danger.
99"Ballistic Advantage"Christoph SchreweT.J. Brady & Rasheed NewsonJanuary 10, 2017 (2017-01-10)1.42[29]
Bob Lee must broker a dangerous exchange in order to save his family. Meanwhile, Nadine struggles to balance her allegiance to Bob Lee and the FBI. Later, Isaac strikes a tenuous deal for his freedom.
1010"Primer Contact"Simon Cellan JonesJohn HlavinJanuary 17, 2017 (2017-01-17)1.45[30]
Bob Lee, Julie, Nadine, and Isaac must work together to breach the Russian Embassy, save Mary, shut down the conspiracy and its remaining players, and prove Bob Lee is innocent once and for all.

text: Season 2 (2017)[edit]

text:
No.overallNo. inseasonTitleDirected byWritten byOriginal air dateU.S. viewers(millions)111"The Hunting Party"Yuval AdlerJohn HlavinJuly 18, 2017 (2017-07-18)1.51[31]
In the season premiere, Bob Lee Swagger and wife Julie join his former Marine unit in Germany and narrowly escape a deadly terrorist attack. FBI Agent Nadine Memphis, meanwhile, takes a job in Washington with Patricia Gregson.
122"Remember the Alamo"Yuval AdlerWill StaplesJuly 25, 2017 (2017-07-25)1.17[32]
Bob Lee investigates the terrorist attack that may have targeted his Marine unit. Memphis helps on the ground in Germany. Flashbacks to Afghanistan help shed light on who might be after them.
133"Don't Mess With Texas"Jaime ReynosoT.J. Brady & Rasheed NewsonAugust 1, 2017 (2017-08-01)1.16[33]
Bob Lee finds Isaac Johnson in Texas after an attempt on his life. Nadine discovers just how much influence Patricia Gregson wields, and a traumatized Julie fights to stay strong for her family.
144"The Dark End of the Street"David StraitonKate BarnowAugust 8, 2017 (2017-08-08)1.27[34]
Bob Lee and Isaac learn the world's greatest assassin is in the U.S. Flashbacks to a mission in Afghanistan reveal his identity: Solotov. Nadine comes to Texas with suspicions of a conspiracy.
155"The Man Called Noon"Lukas EttlinJennifer Cacicio & John HlavinAugust 15, 2017 (2017-08-15)1.19[35]
Bob Lee works to piece together Solotov's motive for targeting their unit. Nadine uncovers a surprise witness to the event that set everything off. Solotov's hunt has him hiding in plain sight.
166"Across the Rio Grande"David StraitonMatthew NewmanAugust 22, 2017 (2017-08-22)1.20[36]
Bob Lee tracks Solotov's money, pitting himself against a Mexican cartel. Nadine helps a journalist investigate a cover-up involving Bob Lee's unit. Julie shoots a guy's ear off with a gun to vent her frustration.
177"Someplace Like Bolivia"Chloe DomontJohn HlavinAugust 29, 2017 (2017-08-29)1.30[37]
Bob Lee and Isaac must team up to escape a Mexican prison before Solotov finds them. As Nadine digs deeper into Atlas, the cover-up points back to Bob Lee's unit. Julie has problems with the law.
188"That'll Be the Day"Jaime ReynosoScott GoldSeptember 5, 2017 (2017-09-05)1.20[38]
Bob Lee tries to draw Solotov into the open, but realizes the Chechen holds the upper hand. Flashbacks reveal the origins of Solotov, while Isaac is courted by his creator in the present.

text: Season 3 (2018)[edit]

text:
No.overallNo. inseasonTitleDirected byWritten byOriginal air dateU.S. viewers(millions)191"Backroads"Jaime ReynosoT.J. Brady & Rasheed NewsonJune 21, 2018 (2018-06-21)0.92[39]
Flashbacks to a childhood trauma plague Bob Lee as he's held hostage with Isaac and Julie in pursuit. Nadine confronts a corrupt senator.
202"Red Meat"David StraitonJohn HlavinJune 28, 2018 (2018-06-28)0.72[40]
Determined to find the truth about his father's death in 1988, Bob Lee starts to investigate. Harris gets dragged into Isaac and Nadine's predicament.
213"Sins of the Father"Amanda MarsalisAmanda SegelJuly 5, 2018 (2018-07-05)0.72[41]
Harris gets on Bob Lee's nerves out on the road as they chase more leads. Nadine and Isaac locate a person of interest who may or may not be friendly.
224"The Importance of Service"Christopher SchreweJennifer CacicioJuly 12, 2018 (2018-07-12)0.77[42]
Bob Lee pays a visit to the Pooles after hearing a new rumour, and Julie follows a lead of her own. Isaac and Nadine pursue an Atlas target.
235"A Call to Arms"David StraitonMatt BosackJuly 19, 2018 (2018-07-19)0.70[43]
A visit to an old friend of his father's leads Bob Lee back to D.C., where he connects with Isaac, Nadine and Harris for a mission at a formal event.
246"Lines Crossed"Jessica LowreyT.J. Brady & Rasheed NewsonJuly 26, 2018 (2018-07-26)0.67[44]
Bob Lee and Isaac visit a man who served with Earl in Vietnam. Nadine takes on a risky mission alone. Julie confronts the Bamas.
257"Swing Vote"Christoph SchreweScott Gold & Tim WalshAugust 2, 2018 (2018-08-02)0.70[45]
Bob Lee and Isaac track down a key contract at a psychiatric facility. Memphis looks for evidence at Gregson's house. Red Jr. makes an offer to Sam.
268"The Red Badge"Chloe DomontJohn HlavinAugust 9, 2018 (2018-08-09)0.71[46]
Bob Lee and Julie discover what Red Jr. wanted from Sam. Red Sr. ends up in a tough spot. Carlita, Harris, Isaac and Nadine plot their next move.
279"Alpha Dog"Hanelle CulpepperAmanda SegelAugust 16, 2018 (2018-08-16)0.79[47]
2810"Orientation Day"David StraitonJennifer Cacicio & Desta Tedros ReffAugust 23, 2018 (2018-08-23)0.70[48]
2911"Family Fire"Ami Canaan MannEric Anderson & Matt BosackAugust 30, 2018 (2018-08-30)0.73[49]
3012"Patron Saint"Millicent SheltonDavid Daitch & Katie Johnson & Matthew NewmanSeptember 6, 2018 (2018-09-06)0.59[50]
3113"Red Light"David StraitonJohn HlavinSeptember 13, 2018 (2018-09-13)0.79[51]

text: Broadcast[edit]

text: Shooter aired on Thursdays at 10:00 pm on USA Network. The episodes are approximately 43 minutes, and are broadcast in both high- and standard definition. In addition, the streaming service Netflix started to broadcast the series in certain regions worldwide, the first season weekly on November 15, 2016, with a one-day delay with respect to the original United States broadcast.[52]

text: Reception[edit]

text: Shooter received mixed reviews from critics. On the review aggregator Rotten Tomatoes, the series has an approval rating of 44%, based on 16 reviews, with an average rating of 5.9/10. The site's critical consensus reads, "Ryan Phillippe's efforts aren't enough to salvage Shooter, a tedious, under-developed drama that lacks an original voice or perspective."[53] On Metacritic, which assigns a normalized rating, the series has a score 60 out of 100, based on 10 critics, indicating "mixed or average reviews".[54]

text: Ratings[edit]

text: Season 1 (2016–17)[edit]

text:
No.

Title

Air date
Rating(18–49)
Viewers(millions)
DVR(18–49)
DVR viewers(millions)
Total(18–49)
Total viewers(millions)

1

"Point of Impact"

November 15, 2016
0.5
1.44[21]
0.3
1.03
0.8
2.47[55]

2

"Exfil"

November 22, 2016
0.4
1.25[22]
0.3
1.15
0.7
2.40[56]

3

"Musa Qala"

November 29, 2016
0.5
1.67[23]
N/A
1.14
N/A
2.81[57]

4

"Overwatch"

December 6, 2016
0.5
1.36[24]
0.3
1.17
0.8
2.53[58]

5

"Recon by Fire"

December 13, 2016
0.4
1.30[25]
0.4
1.29
0.8
2.59[59]

6

"Killing Zone"

December 20, 2016
0.5
1.53[26]
N/A
N/A
N/A
N/A

7

"Danger Close"

December 27, 2016
0.5
1.63[27]
N/A
N/A
N/A
N/A

8

"Red on Red"

January 3, 2017
0.5
1.43[28]
0.4
1.40
0.9
2.83[60]

9

"Ballistic Advantage"

January 10, 2017
0.5
1.42[29]
0.4
1.25
0.9
2.67[61]

10

"Primer Contact"

January 17, 2017
0.5
1.45[30]
0.4
1.35
0.9
2.80[62]

text: Season 2 (2017)[edit]

text:
No.

Title

Air date
Rating(18–49)
Viewers(millions)
DVR(18–49)
DVR viewers(millions)
Total(18–49)
Total viewers(millions)

1

"The Hunting Party"

July 18, 2017
0.4
1.51[31]
0.4
1.26
0.8
2.77[63]

2

"Remember the Alamo"

July 25, 2017
0.3
1.17[32]
N/A
N/A
N/A
N/A

3

"Don't Mess With Texas"

August 1, 2017
0.3
1.16[33]
0.4
1.33
0.7
2.49[64]

4

"The Dark End of the Street"

August 8, 2017
0.3
1.27[34]
0.4
1.17
0.7
2.44[65]

5

"The Man Called Noon"

August 15, 2017
0.3
1.19[35]
0.4
1.27
0.7
2.47[66]

6

"Across the Rio Grande"

August 22, 2017
0.3
1.20[36]
0.4
1.22
0.7
2.42[67]

7

"Someplace Like Bolivia"

August 29, 2017
0.4
1.30[37]
0.3
1.24
0.7
2.55[68]

8

"That'll Be the Day"

September 5, 2017
0.4
1.20[38]
N/A
N/A
N/A
N/A

text: Season 3 (2018)[edit]

text:
No.

Title

Air date
Rating(18–49)
Viewers(millions)
DVR(18–49)
DVR viewers(millions)
Total(18–49)
Total viewers(millions)

1

"Backroads"

June 21, 2018
0.3
0.92[39]
N/A
1.15
N/A
2.07[69]

2

"Red Meat"

June 28, 2018
0.2
0.72[40]
N/A
N/A
N/A
N/A

3

"Sins of the Father"

July 5, 2018
0.2
0.72[41]
N/A
N/A
N/A
N/A

4

"The Importance of Service"

July 12, 2018
0.2
0.77[42]
0.3
1.02
0.5
1.79[70]

5

"A Call to Arms"

July 19, 2018
0.2
0.70[43]
N/A
0.94
N/A
1.64[71]

6

"Lines Crossed"

July 26, 2018
0.2
0.67[44]
N/A
0.90
N/A
1.57[72]

7

"Swing Vote"

August 2, 2018
0.2
0.70[45]
N/A
N/A
N/A
N/A

8

"The Red Badge"

August 9, 2018
0.2
0.71[46]
N/A
N/A
N/A
N/A

9

"Alpha Dog"

August 16, 2018
0.2
0.79[47]
N/A
0.85
N/A
1.64[73]

10

"Orientation Day"

August 23, 2018
0.2
0.70[48]
N/A
N/A
N/A
N/A

11

"Family Fire"

August 30, 2018
0.2
0.73[49]
0.2
0.86
0.4
1.59[74]

12

"Patron Saint"

September 6, 2018
0.1
0.59[50]
0.3
0.90
0.4
1.49[75]

13

"Red Light"

September 13, 2018
0.2
0.79[51]
0.2
0.82
0.4
1.61[76]